Design Store


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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendor
AN 717: Nios II Gen2 Hardware Development Tutorial for Stratix V  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V14.0.0 Intel
AN 720: Simulating the ASMI Block in Your Design  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V14.0.0 Intel
AN 720: Simulating the ASMI Block in Your Design for Arria 10 Device  Design Example \ Outside Design StoreNon kit specific Arria 10 Design ExamplesArria 1014.0.0 Intel
AN 720: Simulating the ASMI Block in Your Design for Arria V GZ Device  Design Example \ Outside Design StoreArria V GZ Development KitArria V14.0.0 Intel
AN 720: Simulating the ASMI Block in Your Design for Cyclone V Device  Design Example \ Outside Design StoreNon kit specific Cyclone V Design ExamplesCyclone V14.0.0 Intel
AN 720: Simulating the ASMI Block in Your Design for Stratix V Device  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V14.0.0 Intel
AN 723: Serial Digital Interface (SDI) II Implementation  Design Example \ Outside Design StoreNon kit specific Arria 10 Design ExamplesArria 1014.0.0 Intel
AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Arria 10 Devices  Design Example \ Outside Design StoreNon kit specific Arria 10 Design ExamplesArria 1015.0.0 Intel
AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor As Control Unit  Design ExampleArria 10 GX FPGA Development KitArria 1015.0.0 Intel
AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note  Design Example \ Outside Design StoreArria 10 GX FPGA Development KitArria 1015.0.0 Intel
AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)  Design Example \ Outside Design StoreNon kit specific Arria 10 Design ExamplesArria 1015.0.0 Intel
AN 756: Altera GPIO to Altera PHYLite Design Implementing Guidelines  Design Example \ Outside Design StoreArria V SoC Development KitArria V15.0.0 Intel
AN 757: 1G/2.5G Ethernet Design Examples  Design Example \ Outside Design StoreArria 10 GX Transceiver Signal Integrity Development KitArria 1015.0.0 Intel
  AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel Stratix 10 Devices  Design ExampleStratix 10 GX FPGA Development KitStratix 1020.4.0 ProIntel
  AN 887: PHY Lite for Parallel Interface Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices  Design ExampleArria 10 GX FPGA Development KitArria 1019.1.0 ProIntel
  AN 888: PHY Lite for Parallel Interface Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices  Design ExampleStratix 10 GX FPGA Development KitStratix 1019.1.0 ProIntel
AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design  Design Example \ Outside Design StoreStratix V GX FPGA Development Kit Stratix V15.0.0 Intel
AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design - Arria 10  Design Example \ Outside Design StoreArria 10 GX FPGA Development KitArria 1015.0.0 Intel
AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design - Arria V  Design Example \ Outside Design StoreArria V GX Starter KitArria V15.0.0 Intel
AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design - Stratix IV  Design Example \ Outside Design StoreStratix IV GX FPGA Development KitStratix IV15.0.0 Intel