| JPEG Decoder Design Example (OpenCL) | Design Example \ Outside Design Store | Non kit specific Stratix V Design Examples | Stratix V | 16.0.0 | Intel | 0 |
| 100Gbps Ethernet PHY only Testbench | Design Example \ Outside Design Store | Non kit specific Stratix V Design Examples | Stratix V | 16.0.2 | Intel | 0 |
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| Accelerated FIR with Built-In Direct Memory Access Example | Design Example | Cyclone V E FPGA Development Kit | Cyclone V | 16.0.0 | Intel | 188 |
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| Adapting Digilent PmodCLP LCD Display to DE10 Lite Development Kit Arduino Shield Header | Design Example | MAX 10 DE10 - Lite | MAX 10 | 16.0.0 | Intel | 134 |
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| ADC and Audio Monitor | Design Example | Odyssey MAX 10 FPGA Kit | MAX 10 | 16.0.0 | Macnica Americas | 102 |
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| ADC Data Capture with Hardware Streaming using ADC Toolkit Display | Design Example | Arrow MAX 10 DECA | MAX 10 | 16.0.0 | Arrow | 201 |
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| ADC Data Capture with Nios II Processor | Design Example | Arrow MAX 10 DECA | MAX 10 | 16.0.0 | Arrow | 264 |
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| ADC example for use with Board Test System Monitor Panel | Design Example | MAX 10 FPGA Development Kit | MAX 10 | 16.0.0 | Intel | 288 |
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| ADC_MIC_LCD | Design Example | MAX 10 NEEK | MAX 10 | 16.0.0 | Terasic | 102 |
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| Altera PHYLite with Dynamic Reconfiguration Loopback Reference Design | Design Example | Arria 10 GX FPGA Development Kit | Arria 10 | 16.0.0 | Intel | 102 |
| AN 680: Product Security Features for Altera Devices | Design Example \ Outside Design Store | Non kit specific Cyclone V Design Examples | Cyclone V | 16.0.0 | Intel | 19 |
| AN 680: Product Security Features for Altera Devices - Arria II | Design Example \ Outside Design Store | Non kit specific Arria II Design Examples | Arria II | 16.0.0 | Intel | 6 |
| AN 680: Product Security Features for Altera Devices - Arria V | Design Example \ Outside Design Store | Non kit specific Arria V Design Examples | Arria V | 16.0.0 | Intel | 10 |
| AN 680: Product Security Features for Altera Devices - Stratix V | Design Example \ Outside Design Store | Non kit specific Stratix V Design Examples | Stratix V | 16.0.0 | Intel | 0 |
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| AN690: PCIe Gen3x8 AVMM DMA with On-Chip Memory | Design Example | Arria 10 GX FPGA Development Kit | Arria 10 | 16.0.2 | Intel | 62 |
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| AN708: PCIe Gen3x8 AVMM DMA with External Memory | Design Example | Arria 10 GX FPGA Development Kit | Arria 10 | 16.0.2 | Intel | 63 |
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| Arria 10 Configuration via PCIe Init reference design | Design Example | Arria 10 GX FPGA Development Kit | Arria 10 | 16.0.0 | Intel | 132 |
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| Arria 10 DisplayPort 4KP60 with Video and Image Processing Pipeline Re-Transmit Reference Design | Design Example | Arria 10 GX FPGA Development Kit | Arria 10 | 16.0.0 | Intel | 206 |
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| Arria 10 FPGA Dev Kit Baseline Pinout | Design Example | Arria 10 GX FPGA Development Kit | Arria 10 | 16.0.0 | Intel | 77 |
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| Arria 10 FPGA Dev Kit ES2 Baseline Design | Design Example | Arria 10 GX FPGA Development Kit | Arria 10 | 16.0.0 | Intel | 46 |
